A Pipeline Chip for Quasi Arithmetic Coding

• WISEMAN Yair

  The Department of Math and Computer Science, Bar-llan University

抄録

A combination of a software and a systolic hardware implementation for the Quasi Arithmetic sompression algorithm is presented. The hardware is implemented as a pipeline hardware implementation. The implementation doesn't change the the algorithm. It just split it into two parts. The combination of parallel software and pipeline hardware can give very fast compression without decline of the compression efficiency.

収録刊行物

• IEICE transactions on fundamentals of electronics, communications and computer sciences

  IEICE transactions on fundamentals of electronics, communications and computer sciences 84 (4), 1034-1041, 2001-04-01

  一般社団法人電子情報通信学会

キーワード

• pipeline structure
• compression
• arithmetic coding
• hardware-software combination

詳細情報

• CRID: 1570291227426950272
• NII論文ID: 110003208901
• NII書誌ID: AA10826239
• ISSN: 09168508
• 本文言語コード: en
• データソース種別:
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