Satsuki: An Integrated Processor Synthesis and Compiler Generation System

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Entire systems on a chip (SOCs) embodying a processor, memory, and system-specific peripheral hardware are now an everyday reality. The current generation of SOC designers are driven more than ever by the need to lower chip cost, while at the same time being faced with demands to get designs to market more quickly. It was to support this new community of designers that we developed Satsuki-an integrated processor synthesis and compiler generation system. By allowing the designer to tune the processor design to the bit-width and performance required by the application, minimum cost designs are achieved. Using synthesis to implement the processor in the same technology as the rest of the chip, allows for global chip optimization from the perspective of the system as a whole and assures design portability. The integral compiler generator, driven by the same parameters used for processor synthesis, promotes high-level expression of application algorithms while at the same time isolating the application software from the processor implementation. Synthesis experiments incorporating a 0.8 micron CMOS gate array have produced designs ranging from a 45MHz, 1,500 gate, 8-bit processor with a 4-word register file to a 31MHz, 9,800 gate, 32-bit processor with a 16-word register file.

収録刊行物

  • IEICE transactions on information and systems

    IEICE transactions on information and systems 79(10), 1373-1381, 1996-10-25

    一般社団法人電子情報通信学会

参考文献:  16件中 1-16件 を表示

被引用文献:  8件中 1-8件 を表示

各種コード

  • NII論文ID(NAID)
    110003209585
  • NII書誌ID(NCID)
    AA10826272
  • 本文言語コード
    ENG
  • 資料種別
    ART
  • ISSN
    09168532
  • データ提供元
    CJP書誌  CJP引用  NII-ELS 
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