Embedded System Cost Optimization via Data Path Width Adjustment

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抄録

Entire systems embedded in a chip and consisting of a processor, memory, and system-specific peripheral hardware are now commonly contained in commodity electronic de-vices. Cost minimization of these systems is of paramount economic importance to manufactures of these devices. By employing a variable configuration processor in conjunction with a multi-precision compiler generator, we show that there are situations in which considerable system cost reduction can be obtained by synthesizing a CPU that is narrower than the largest variable in the application program.

収録刊行物

  • IEICE transactions on information and systems

    IEICE transactions on information and systems 80(10), 974-981, 1997-10-25

    一般社団法人電子情報通信学会

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被引用文献:  11件中 1-11件 を表示

各種コード

  • NII論文ID(NAID)
    110003209804
  • NII書誌ID(NCID)
    AA10826272
  • 本文言語コード
    ENG
  • 資料種別
    ART
  • ISSN
    09168532
  • データ提供元
    CJP書誌  CJP引用  NII-ELS 
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