Design of C-Testable Modified-Booth Multipliers

• BOATENG Kwame Osei

  Faculty of Engineering, Ehime University

• TAKAHASHI Hiroshi

  Faculty of Engineering, Ehime University

• TAKAMATSU Yuzo

  Faculty of Engineering, Ehime University

抄録

In this paper, we consider the design for testability of multiplier based on the modified Booth Algorithm. First, we present a basic array implementation of the multiplier. Next, we introduce testability considerations to derive two C-testable designs. The first of the designs is C-testable under the single stuck-at fault model(SAF)with 10 test patterns. And, the second is C-testable under the cell fault model(CFM)with 33 test patterns.

収録刊行物

• IEICE transactions on information and systems

  IEICE transactions on information and systems 83 (10), 1868-1878, 2000-10-25

  一般社団法人電子情報通信学会

キーワード

• multiplier
• modified Booth Algorithm
• design for testability (DFT)
• C-testable design

詳細情報

• CRID: 1570291227534970368
• NII論文ID: 110003210198
• NII書誌ID: AA10826272
• ISSN: 09168532
• 本文言語コード: en
• データソース種別:
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