A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector

• KONDOH Harufusa

  System LSI Laboratory, Mitsubishi Electric Corporation

• NOTANI Hiromi

  System LSI Laboratory, Mitsubishi Electric Corporation

• YOSHIMURA Tsutomu

  System LSI Laboratory, Mitsubishi Electric Corporation

• SHIBATA Hiroshi

  Institute of Technology, Mitsubishi Electric Corporation

• MATSUDA Yoshio

  System LSI Laboratory, Mitsubishi Electric Corporation

抄録

A new approach which implements a simple, high-speed phase detector with precharge logic will be presented. The minimum detectable phase difference is 40 psec, which is less than a half of conventional detectors. A current mode ring oscillator with a complementary-input bias generator has also been developed to enhance the dynamic range of the VCO under a low supply voltage. A fully CMOS PLL was designed using 0.5-μm technology. By virtue of this simple, fast detector, the wide operation range of 250 MHz at 1.5 V to 622 MHz at 3.0 V was achieved by simulation.

収録刊行物

• IEICE transactions on electronics

  IEICE transactions on electronics 78 (4), 381-388, 1995-04-20

  一般社団法人電子情報通信学会

キーワード

• PLL
• PFD
• VCO
• CMOS
• ATM

詳細情報

• CRID: 1572543027348730112
• NII論文ID: 110003210861
• NII書誌ID: AA10826283
• ISSN: 09168524
• 本文言語コード: en
• データソース種別:
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