Evaluation of Fixed Charge and Interface Trap Densities in SIMOX Wafers and Their Effects on Device Characteristics

• MASUI Shoichi

  the Advanced Technology Research Laboratories, Nippon Steel Corporation

• NAKAJIMA Tatsuo

  the Advanced Technology Research Laboratories, Nippon Steel Corporation

• KAWAMURA Keisuke

  the Advanced Technology Research Laboratories, Nippon Steel Corporation

• YANO Takayuki

  the Advanced Technology Research Laboratories, Nippon Steel Corporation

• HAMAGUCHI Isao

  the Advanced Technology Research Laboratories, Nippon Steel Corporation

• TACHIMORI Masaharu

  the Advanced Technology Research Laboratories, Nippon Steel Corporation

抄録

The buried oxide nonintegrities, represented as the equivalent fixed oxide charge and interface trap densities at both the upper and lower interface of buried oxide, are evaluated for low-dose and high-dose SIMOX wafers, and their effects on device characteristics are investigated. The equivalent fixed oxide charge and trap densities at the lower interface, which are measured with buried oxide capacitors, are negligibly small in as-fabricated SIMOX wafers. This result enables us to make an analytical model of the parasitic drain/source-to-substrate capacitance in an SOI MOSFET, in which the effect of the depletion layer under the buried oxide is considered. The influence of thinner buried oxide and process-induced fixed oxide charge on the parasitic capacitance is explored with this model. The equivalent fixed oxide charge and trap densities at the upper interface are evaluated by the threshold voltage measurement in an SOI NMOSFET. The principle of this evaluation as well as the experimental technique are described in detail. The oxide charge and trap densities at the upper interface are higher than those at the lower interface for both SIMOX wafers. With a new model of the subthreshold slope based on a two-dimensional potential analysis the influence of the trap at the upper interface is discussed.

収録刊行物

• IEICE transactions on electronics

  IEICE transactions on electronics 78 (9), 1263-1272, 1995-09-25

  一般社団法人電子情報通信学会

キーワード

• SOI
• fixed oxide charge
• interface trap
• parasitic capacitance
• subthreshold slope

詳細情報

• CRID: 1573105977302110720
• NII論文ID: 110003210967
• NII書誌ID: AA10826283
• ISSN: 09168524
• 本文言語コード: en
• データソース種別:
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