A New Hierarchical RSM for TCAD-Based Device Design in 0.4μm CMOS Development

• SATO Hisako

  Hitachi, Ltd. Device Development Center

• TSUNENO Katsumi

  Hitachi, Ltd. Device Development Center

• AOYAMA Kimiko

  Hitachi, Ltd. Device Development Center

• NAKAMURA Takahide

  Hitachi, Ltd. Device Development Center

• KUNITOMO Hisaaki

  Hitachi Micro-computer System, Ltd.

• MASUDA Hiroo

  Hitachi, Ltd. Device Development Center

抄録

A new methodology for simulation-based CMOS process design has been proposed, using a Hierarchical Response Surface Method (HRSM) and an efficient experimental calibration. The design methodology has been verified using a 0.4 micron CMOS process. The proposed HRSM achieved a 60% reduction of process and device design cost in comparison with those of conventional TCAD. The procedure was performed in conjunction with an experimental calibration technique to provide a reliable threshold voltage prediction including process variation effects. The total CPU cost was 200 hr. on SUN SPARC 10 and the error of the predicted threshold voltage was less than 0.02 V.

収録刊行物

• IEICE transactions on electronics

  IEICE transactions on electronics 79 (2), 226-233, 1996-02-25

  一般社団法人電子情報通信学会

キーワード

• TCAD
• RSM
• CMOS design

詳細情報

• CRID: 1571135652464275200
• NII論文ID: 110003211009
• NII書誌ID: AA10826283
• ISSN: 09168524
• 本文言語コード: en
• データソース種別:
  • CiNii Articles