Single-Electron Majority Logic Circuits

• IWAMURA Hiroki

  Faculty of Engineering, Hokkaido University

• AKAZAWA Masamichi

  Faculty of Engineering, Hokkaido University

• AMEMIYA Yoshihito

  Faculty of Engineering, Hokkaido University

抄録

This paper proposes an architecture for circuit construction for developing single-electron integrated circuits based on majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. It accepts an odd number of inputs and produces the corresponding output on the basis of the principle of majority decision; it produces an output of logic "1" if the majority of the inputs is 1, and an output of "0" if the majority is 0. By combining the proposed majority gate circuits, various subsystems can be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation error induced by thermal agitation is also estimated.

収録刊行物

• IEICE transactions on electronics

  IEICE transactions on electronics 81 (1), 42-48, 1998-01-25

  一般社団法人電子情報通信学会

キーワード

• single electron majority
• logic threshold logic
• gate
• circuit
• thermal noise

詳細情報

• CRID: 1571698602419019776
• NII論文ID: 110003211342
• NII書誌ID: AA10826283
• ISSN: 09168524
• 本文言語コード: en
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