Megabit - Class Size - Configurable 250 - MHz SRAM Macrocells with a Squashed - Memory - Cell Architecture

• SHIBATA Nobutara

  the NTT System Electronics Laboratories

• INOKAWA Hiroshi

  the NTT Electronics Co., Ltd

• TOKUNAGA Keiichiro

  the NTT Electronics Co., Ltd

• OHTA Soichi

  the NTT Advanced Technology Co., Ltd

抄録

High-speed and low-power techniques are described for megabit-class size-configurable CMOS SRAM macro-cells. To shorten the design turn-around-time, the methodology of abutting nine kinds of leaf cells is employed; two-level via-hole programming and the array-address decoder embedded in each control leaf cell present a divided-memory-array structure. A new squashed-memory-cell architecture using trench isolation and stacked-via-holes is proposed to reduce access times and power dissipation. To shorten the time for writing data, per-bitline architecture is proposed, in which every bitline has a personal writing driver. Also, read-out circuitry using a current-sense-type two-stage sense amplifier is designed. The effect of the non-multiplexed bitline scheme for fast read-out is shown in a simulation result. To reduce the noise from the second to first-stage amplifier due to a feedback loop, current paths are separated so as not to cause common impedance. To confirm the techniques described in this paper, a 1-Mb SRAM test chip was fabricated with an advanced 0.35-μm CMOS/bulk process. The SRAM has demonstrated 250-MHz operation with a 2.5-V typical power supply. Also, 100-mW power dissipation was obtained at a practical operating frequency of 150-MHz.

収録刊行物

• IEICE transactions on electronics

  IEICE transactions on electronics 82 (1), 94-104, 1999-01-25

  一般社団法人電子情報通信学会

キーワード

• SRAM
• macrocell
• size-configurable
• high-speed
• low-power
• per-bitline architecture
• current-sense amplefier
• squashed memory cell
• trench isolation

詳細情報

• CRID: 1570291227534216960
• NII論文ID: 110003211566
• NII書誌ID: AA10826283
• ISSN: 09168524
• 本文言語コード: en
• データソース種別:
  • CiNii Articles