An Area-Effective Datapath Architecture for Embedded Microprocessors and Scalable Systems

• INOUE Toshiaki

  Silicon System Research Laboratories, System Devices and Fundamental Research, NEC Corpration

• MANABE Takashi

  Production Technology Laboratories, Prototype Engineering Center, NEC Corpration

• TORII Sunao

  Silicon System Research Laboratories, System Devices and Fundamental Research, NEC Corpration

• MATSUSHITA Satoshi

  Silicon System Research Laboratories, System Devices and Fundamental Research, NEC Corpration

• EDAHIRO Masato

  Silicon System Research Laboratories, System Devices and Fundamental Research, NEC Corpration

• NISHI Naoki

  Silicon System Research Laboratories, System Devices and Fundamental Research, NEC Corpration

• MAYASINA Masakazu

  Silicon System Research Laboratories, System Devices and Fundamental Research, NEC Corpration

Abstract

We have proposed area-reduction techniques for superscalar datapath architectures with 34 SIMD instructions and have developed an integer-media unit based on these techniques. The unit's design is both functionally asymmetrical and integer-SIMD unified, and the resulting savings in area are 27%-48% as compared to other, functionally equivalent mid-level microprocessor designs, with performance that is, at most, only 7.2% lower. Further, in 2-D IDCT processing, the unit outperforms embedded microprocessor designs without SIMD functions by 49%-118%. Specifically, effective area reduction of adders, shifters, and multiply-and-adders has been achieved by using the unified design. These area-effective techniques are useful for embedded microprocessors and scalable systems that employ highly parallel superscalar and on-chip parallel architectures. The integer-media unit has been implemented in an evaluation chip fabricated with 0.15-μm 5-metal CMOS technology.

Journal

• IEICE transactions on electronics

  IEICE transactions on electronics 84 (8), 1014-1020, 2001-08-01

  The Institute of Electronics, Information and Communication Engineers

Keywords

• SIMD
• multiplier
• embedded microprocessors
• onchip multiprocessor
• area-efficiency

Details

• CRID: 1573387452279451648
• NII Article ID: 110003212269
• NII Book ID: AA10826283
• ISSN: 09168524
• Text Lang: en
• Data Source:
  • CiNii Articles