Impacts of Compiler Optimizations on Address Bus Energy : An Empirical Study

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著者

    • TOMIYAMA Hiroyuki
    • Department of Information Engineering, the Graduate School of Information Science, Nagoya University

抄録

Energy consumption is one of the most critical constraints in the design of portable embedded systems. This paper describes an empirical study about the impacts of compiler optimizations on the energy consumption of the address bus between processor and instruction memory. Experiments using a number of real-world applications are presented, and the results show that transitions on the instruction address bus can be significantly reduced (by 85% on the average) by the compiler optimizations together with bus encoding.

収録刊行物

  • IEICE transactions on fundamentals of electronics, communications and computer sciences

    IEICE transactions on fundamentals of electronics, communications and computer sciences 87(10), 2815-2820, 2004-10-01

    一般社団法人電子情報通信学会

参考文献:  14件中 1-14件 を表示

各種コード

  • NII論文ID(NAID)
    110003212809
  • NII書誌ID(NCID)
    AA10826239
  • 本文言語コード
    ENG
  • 資料種別
    SHO
  • ISSN
    09168508
  • データ提供元
    CJP書誌  NII-ELS  IR 
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