Dynamically Reconfigurable Processor Implemented with IPFlex's DAPDNA Technology

• SUGAWARA Takayuki

  IPFlex Inc.

• IDE Keisuke

  IPFlex Inc.

• SATO Tomoyoshi

  IPFlex Inc.

抄録

The DAPDNA[○!R]-2 is the world's first general purpose dynamically reconfigurable processor for commercial usage. It is a dual-core processor consisting of a custom RISC core called the Digital Application Processor (DAP), and a two dimensional array of dynamically reconfigurable processing elements referred to as the Distributed Network Architecture (DNA). The DAP has a 32 bit instruction set architecture with an 8 KB instruction cache and 8 KB data cache that can be accessed in one clock cycle. It has an interrupt control function to detect data processing completion in the DNA-Matrix. The DNA-Matrix has different types of data processing elements such as ALU, delay, and memory elements to process fully parallel computations. The DNA-Matrix includes 32 independent 16KB high speed SRAM elements (in total 512KB). The DNA-Matrix, even with its parallel computational capability, can be synchronized and co-work at the same clock frequency as the DAP. The processor operates at a 166 MHz working frequency and fabricated with a 0.11 μm CMOS process. The DAPDNA-2 device can be connected directly with up to 16 units with linear scalability in processing performance, provided the bandwidth requirement is within the maximum communication speed between DNAs, which is 32 Gbps. The DAPDNA-2 performs at a level that is two orders of magnitude higher than conventional high performance processors

収録刊行物

• IEICE transactions on information and systems

  IEICE transactions on information and systems 87 (8), 1997-2003, 2004-08-01

  一般社団法人電子情報通信学会

キーワード

• dynamically reconfigurable processor
• coarse-grain processing element
• heterogeneous two-dimensional array
• spatial computing
• temporal computing

詳細情報

• CRID: 1574231877208066048
• NII論文ID: 110003214090
• NII書誌ID: AA10826272
• ISSN: 09168532
• 本文言語コード: en
• データソース種別:
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