A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition

• TOGAWA Nozomu

  Department of Computer Science, Waseda University

• TACHIKAKE Koichi

  Department of Computer Science, Waseda University

• MIYAOKA Yuichiro

  Department of Computer Science, Waseda University

• YANAGISAWA Masao

  Department of Computer Science, Waseda University

• OHTSUKI Tatsuo

  Department of Computer Science, Waseda University

抄録

This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a timing constraint, the proposed algorithm synthesizes an area-optimized processor core with optimal SIMD functional units. It also synthesizes a SIMD instruction set. The input initial assembly code is assumed to run on a full-resource SIMD processor (virtual processor) which has all the possible SIMD functional units. In our algorithm, we introduce the SIMD operation decomposition and apply it to the initial assembly code and the full-resource SIMD processor. By gradually reducing SIMD operations or decomposing SIMD operations, we can finally find a processor core with small area under the given timing constraint. The promising experimental results are also shown.

収録刊行物

• IEICE transactions on information and systems

  IEICE transactions on information and systems 88 (7), 1340-1349, 2005-07-01

  一般社団法人電子情報通信学会

キーワード

• processor synthesis
• instruction set synthesis
• packed SIMD-type functional unit
• packed SIMD-type instruction
• hardware
• software cosynthesis

詳細情報

• CRID: 1573105977301282560
• NII論文ID: 110003214320
• NII書誌ID: AA10826272
• ISSN: 09168532
• 本文言語コード: en
• データソース種別:
  • CiNii Articles