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- SUZUKI Toshihide
- Fujitsu Laboratories Ltd.
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- NAKASHA Yasuhiro
- Fujitsu Laboratories Ltd.
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- KANO Hideki
- Fujitsu Laboratories Ltd.
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- SATO Masaru
- Fujitsu Laboratories Ltd.
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- MASUDA Satoshi
- Fujitsu Laboratories Ltd.
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- SAWADA Ken
- Fujitsu Laboratories Ltd.
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- MAKIYAMA Kozo
- Fujitsu Laboratories Ltd.
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- TAKAHASHI Tsuyoshi
- Fujitsu Laboratories Ltd.
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- HIROSE Tatsuya
- Fujitsu Laboratories Ltd.
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- HARA Naoki
- Fujitsu Laboratories Ltd.
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- TAKIGAWA Masahiko
- Fujitsu Laboratories Ltd.
この論文をさがす
抄録
In this paper, we describe the operation of circuits capable of more than 40-Gbit/s that we have developed using InP HEMT technology. For example, we succeeded in obtaining 43-Gbit/s operation for a full-rate 4 1Multiplier (MUX), 50-Gbit/s operation for a Demultiplexer (DEMUX), 50-Gbit/s operation for a D-type flip-flop (D-FF), and a preamplifier with a bandwidth of 40 GHz. In addition, the achievement of 90-Gbit/s operation for a 2・1MUX and a distributed amplifier with over 110-GHz bandwidth indicates that InP HEMT technology is promising for system operations of over 100 Gbit/s. To achieve these results, we also developed several design techniques to improve frequency response above 80 GHz including a symmetric and separated layout of differential elements in the basic SCFL gate and inverted microstrip.
収録刊行物
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- IEICE transactions on electronics
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IEICE transactions on electronics 86 (10), 1916-1922, 2003-10-01
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詳細情報 詳細情報について
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- CRID
- 1571698602418878976
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- NII論文ID
- 110003214485
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- NII書誌ID
- AA10826283
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- ISSN
- 09168524
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- 本文言語コード
- en
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- データソース種別
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- CiNii Articles