Fast Learning Algorithms for Self-Organizing Map Employing Rough Comparison WTA and its Digital Hardware Implementation

• TAMUKOH Hakaru

  Graduate School of Life Science and Systems Engineering, Kyushu Institute of Technology

• HORIO Keiichi

  Graduate School of Life Science and Systems Engineering, Kyushu Institute of Technology

• YAMAKAWA Takeshi

  Graduate School of Life Science and Systems Engineering, Kyushu Institute of Technology

抄録

This paper describes a new fast learning algorithm for Self-Organizing Map employing a "rough comparison winner-take-all" and its digital hardware architecture. In rough comparison winner-take-all algorithm, the winner unit is roughly and strictly assigned in early and later learning stage, respectively. It realizes both of high accuracy and fast learning. The digital hardware of the self-organizing map with proposed WTA algorithm is implemented using FPGA. Experimental results show that the designed hardware is superior to other hardware with respect to calculation speed.

収録刊行物

• IEICE transactions on electronics

  IEICE transactions on electronics 87 (11), 1787-1794, 2004-11-01

  一般社団法人電子情報通信学会

キーワード

• self-organizing map
• fast learning algorithm
• rough comparison winner-take-all
• hardware architecture

詳細情報

• CRID: 1572543027347942400
• NII論文ID: 110003214792
• NII書誌ID: AA10826283
• ISSN: 09168524
• 本文言語コード: en
• データソース種別:
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