A Single-Electron-Transistor Logic Gate Family for Binary, Multiple-Valued and Mixed-Mode Logic(<Special Section>New System Paradigms for Integrated Electronics)

この論文にアクセスする

この論文をさがす

著者

    • DEGAWA Katsuhiko
    • Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku University
    • AOKI Takafumi
    • Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku University
    • HIGUCHI Tatsuo
    • Department of Electronics, Faculty of Engineering, Tohoku Institute of Technology
    • TAKAHASHI Yasuo
    • Graduate School of Information Science and Technology, Hokkaido University

抄録

This paper presents a model-based study of SET (Single-Electron-Transistor) logic gate family for synthesizing binary, MV (Multiple-Valued) and mixed-mode logic circuits. The use of SETs combined with MOS transistors allows compact realization of basic logic functions that exhibit periodic transfer characteristics. The operation of basic SET logic gates is successfully confirmed through SPICE circuit simulation based on the physical device model of SETs. The proposed SET logic gates are useful for implementing binary logic circuits, MV logic circuits and binary-MV mixed-mode logic circuits in a highly flexible manner. As an example, this paper describes design of various parallel counters for carry-propagation-free arithmetic, where MV signals are effectively used to achieve higher functionality with lower hardware complexity.

収録刊行物

  • IEICE transactions on electronics   [巻号一覧]

    IEICE transactions on electronics E87-C(11), 1827-1836, 2004-11-01  [この号の目次]

    一般社団法人電子情報通信学会

参考文献:  13件

参考文献を見るにはログインが必要です。ユーザIDをお持ちでない方は新規登録してください。

被引用文献:  4件

被引用文献を見るにはログインが必要です。ユーザIDをお持ちでない方は新規登録してください。

各種コード

  • NII論文ID(NAID)
    110003214798
  • NII書誌ID(NCID)
    AA10826283
  • 本文言語コード
    ENG
  • 資料種別
    ART
  • ISSN
    09168524
  • データ提供元
    CJP書誌  CJP引用  NII-ELS 
ページトップへ