A Single-Electron-Transistor Logic Gate Family for Binary, Multiple-Valued and Mixed-Mode Logic(<Special Section>New System Paradigms for Integrated Electronics)

    • DEGAWA Katsuhiko
    • Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku University
    • AOKI Takafumi
    • Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku University
    • HIGUCHI Tatsuo
    • Department of Electronics, Faculty of Engineering, Tohoku Institute of Technology

    • TAKAHASHI Yasuo
    • Graduate School of Information Science and Technology, Hokkaido University

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Abstract

This paper presents a model-based study of SET (Single-Electron-Transistor) logic gate family for synthesizing binary, MV (Multiple-Valued) and mixed-mode logic circuits. The use of SETs combined with MOS transistors allows compact realization of basic logic functions that exhibit periodic transfer characteristics. The operation of basic SET logic gates is successfully confirmed through SPICE circuit simulation based on the physical device model of SETs. The proposed SET logic gates are useful for implementing binary logic circuits, MV logic circuits and binary-MV mixed-mode logic circuits in a highly flexible manner. As an example, this paper describes design of various parallel counters for carry-propagation-free arithmetic, where MV signals are effectively used to achieve higher functionality with lower hardware complexity.

Journal

IEICE transactions on electronics   [List of Volumes]

IEICE transactions on electronics E87-C(11), 1827-1836, 2004-11-01  [Table of Contents]

The Institute of Electronics, Information and Communication Engineers

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Cited by:  4

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Codes

  • NII Article ID (NAID) :
    110003214798
  • NII NACSIS-CAT ID (NCID) :
    AA10826283
  • Text Lang :
    ENG
  • Article Type :
    Journal Article
  • ISSN :
    09168524
  • Databases :
    CJP  CJPref  NII-ELS