Memory Data Organization for Low-Energy Address Buses

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著者

    • TOMIYAMA Hiroyuki
    • Department of Information Engineering, the Graduate School of Information Science, Nagoya University
    • TAKADA Hiroaki
    • Department of Information Engineering, the Graduate School of Information Science, Nagoya University
    • DUTT Nikil D.
    • Center of Embedded Computer Systems, University of California

抄録

Energy consumption has become one of the most critical constraints in the design of portable multimedia systems. For media applications, address buses between processor and data memory consume a considerable amount of energy due to their large capacitance and frequent accesses. This paper studies impacts of memory data organization on the address bus energy. Our experiments show that the address bus activity is significantly reduced by 50% through exploring memory data organization and encoding address buses.

収録刊行物

  • IEICE transactions on electronics

    IEICE transactions on electronics 87(4), 606-612, 2004-04-01

    一般社団法人電子情報通信学会

参考文献:  19件中 1-19件 を表示

被引用文献:  1件中 1-1件 を表示

各種コード

  • NII論文ID(NAID)
    110003214897
  • NII書誌ID(NCID)
    AA10826283
  • 本文言語コード
    ENG
  • 資料種別
    ART
  • ISSN
    09168524
  • データ提供元
    CJP書誌  CJP引用  NII-ELS  IR 
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