Charging and Discharging Characteristics of Stacked Floating Gates of Silicon Quantum Dots

• SHIBAGUCHI Taku

  Graduate School of Advanced Sciences and Matters, Hiroshima University

• IKEDA Mitsuhisa

  Graduate School of Advanced Sciences and Matters, Hiroshima University

• MURAKAMI Hideki

  Graduate School of Advanced Sciences and Matters, Hiroshima University

• MIYAZAKI Seiichi

  Graduate School of Advanced Sciences and Matters, Hiroshima University

抄録

We have fabricated Al-gate MOS capacitors with a Si quantum-dots (Si-QDs) floating gate, the number of dots was changed in the range of 1.6-4.8×10^<11>cm^<-2> in areal density with repeating the formation of Si dots and their surface oxidation a couple of times. The capacitance-voltage (C-V) characteristics of Si-QDs floating gate MOS capacitors on p-Si(100) confirm that, with increasing number of dots density, the flat-band voltage shift due to electron charging in Si-QDs is increased and the accumulation capacitance is decreased. Also, in the negative bias region beyond the flat-band condition, the voltage shift in the C-V curves due to the emission of valence electrons from intrinsic Si-QDs was observed with no hysterisis presumably because holes generated in Si-QDs can smoothly recombine with electrons tunneling through the 2.8 nm-thick bottom SiO_2. In addition, we have demonstrated the charge retention characteristic improves in the Si-QDs stacked structure.

収録刊行物

• IEICE transactions on electronics

  IEICE transactions on electronics 88 (4), 709-712, 2005-04-01

  一般社団法人電子情報通信学会

キーワード

• silicon quantum dot
• MOS memory
• floating gate
• Coulomb blockade

詳細情報

• CRID: 1573105977302031616
• NII論文ID: 110003215182
• NII書誌ID: AA10826283
• ISSN: 09168524
• 本文言語コード: en
• データソース種別:
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