COACH : A computer aided design tool for computer architectures

• AKABOSHI H.

  the Interdisciplinary Graduate School of Engineer Sciences, Kyushu University

• Yasuura Hiroto

  the Interdisciplinary Graduate School of Engineer Sciences, Kyushu University

抄録

A modern architect can not design high performance computer architecture without thinking all factors of performance from hardware level (logic / layout design) to system level (application programs, operating systems, and compilers). For computer architecture design, there are few practical CAD tools, which support design activities of the architect. In this paper, we propose a CAD tool, called COACH, for computer architecture design. COACH supports architecture design from hardware level to system level. To make a high-performance general purpose computer system, the architect evaluates system performance as well as hardware level performance. To evaluate hardware level performance accurately, logic / layout synthesis tools and simulator are used for evaluation. Logic / layout synthesis tools translate the architecture design into logic circuits and layout pattern and simulator is used to get accurate information on hardware level performance which consists of clock frequency, the number of transistors, power consumption, and so on. To evaluate system level performance, a compiler generator is introduced. The compiler generator generates a compiler of a programming language from the description of architecture design. The designed architecture is simulated in the behavior level with programs compiled by the compiler, and the architect can get information on system level performance which consists of program execution steps, etc. From both hardware level performance and system level performance, the architect can evaluate and revise his / her architecture, considering the architecture from hardware level to system level. In this paper, we propose a new design methodology which uses (I) logic / layout synthesis tools and simulators as tools for architecture design and (II) a compiler generator for system level evaluation. COACH, a CAD system based on the methodology, is discussed and a prototype of COACH is implemented. Using the design methodology, two processors are designed. The result of the designs shows that the proposed design methodology are effective in architecture design.

収録刊行物

• IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, A

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, A 76 (10), 1760-1769, 1993

  一般社団法人電子情報通信学会

キーワード

• computer aided design
• computer architecture design
• performance evaluation
• compiler generation

詳細情報

• CRID: 1570854177487910656
• NII論文ID: 110003215405
• NII書誌ID: AA10826239
• ISSN: 09168508
• 本文言語コード: en
• データソース種別:
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