Single Chip Implementation of MPEG2 Decoder for HDTV Level Pictures

• ONOYE Takao

  Faculty of Engineering, Osaka University

• MASAKI Toshihiro

  Faculty of Engineering, Osaka University

• MORIMOTO Yasuo

  Faculty of Engineering, Osaka University

• SATO Yoh

  Faculty of Engineering, Osaka University

• SHIRAKAWA Isao

  Faculty of Engineering, Osaka University

• MATSUMURA Kenji

  K. C. S. Co., Ltd.

抄録

A single chip MPEG2 MP@HL video decoder has been developed, which consists mainly of specific functional units and macroblock level pipeline buffers. A new organization is also devised for a set of off-chip frame memories and the interfaces associated with it. Owing to sophisticated I/O interfaces among functional units, the macroblock level pipeline in conjunction with different decoding facilities attains a high throughput to such an extent as to decode HDTV images in real time. Moreover, a set of these functional units, pipeline buffers, and frame memory interfaces, together with a sequence controller, is integrated for the first time in a single chip, which has the total area of 8.8×9.2 mm^2 with a 0.6 μm triple-metal CMOS technology, and dissipates 1.2 W from a single 3.3 V supply.

収録刊行物

• IEICE transactions on fundamentals of electronics, communications and computer sciences

  IEICE transactions on fundamentals of electronics, communications and computer sciences 79 (3), 330-338, 1996-03-25

  一般社団法人電子情報通信学会

キーワード

• MPEG2
• HDTV
• VLSI
• decoder
• ASIC

詳細情報

• CRID: 1572543027348277248
• NII論文ID: 110003216157
• NII書誌ID: AA10826239
• ISSN: 09168508
• 本文言語コード: en
• データソース種別:
  • CiNii Articles