Module Selection Using Manufacturing Information

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著者

    • TOMIYAMA Hiroyuki
    • the Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyusyu University
    • YASUURA Hiroto
    • the Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyusyu University

抄録

Since manufacturing processes inherently fluctuate. LSI chips which are produced from the same design have different propagation delays. However, the difference in delays caused by the process fluctuation has rarely been considered in most of existing high-level synthesis systems. This paper presents a new approach to module selection in high-level synthesis, which exploits the difference in functional unit delays. First, a module library model which assumes the probabilistic nature of functional unit delays is presented. Then, we propose a module selection problem and an algorithm which minimizes the cost per faultless chip. Experimental results demonstrate that the proposed algorithm finds optimal module selections which would not have been explored without manufacturing information.

収録刊行物

  • IEICE transactions on fundamentals of electronics, communications and computer sciences

    IEICE transactions on fundamentals of electronics, communications and computer sciences 81(12), 2576-2584, 1998-12-01

    一般社団法人電子情報通信学会

参考文献:  17件中 1-17件 を表示

被引用文献:  1件中 1-1件 を表示

各種コード

  • NII論文ID(NAID)
    110003216442
  • NII書誌ID(NCID)
    AA10826239
  • 本文言語コード
    ENG
  • 資料種別
    ART
  • ISSN
    09168508
  • データ提供元
    CJP書誌  CJP引用  NII-ELS 
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