Instruction Scheduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches

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著者

    • TOMIYAMA Hiroyuki
    • Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyusyu University
    • ISHIHARA Tohru
    • Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyusyu University
    • INOUE Akihiko
    • Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyusyu University
    • YASUURA Hiroto
    • Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyusyu University

抄録

In many embedded systems, a significant amount of power is consumed for off-chip driving because off-chip capacitances are much larger than on-chip capacitances. This paper proposes instruction scheduling techniques to reduce power consumed for off-chip driving. The techniques minimize the switching activity of a data bus between an on-chip cache and amain memory when instuction cache misses occur. The scheduling problem is formulated and two scheduling algorithms are presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithms.

収録刊行物

  • IEICE transactions on fundamentals of electronics, communications and computer sciences

    IEICE transactions on fundamentals of electronics, communications and computer sciences 81(12), 2621-2629, 1998-12-01

    一般社団法人電子情報通信学会

参考文献:  19件中 1-19件 を表示

各種コード

  • NII論文ID(NAID)
    110003216447
  • NII書誌ID(NCID)
    AA10826239
  • 本文言語コード
    ENG
  • 資料種別
    ART
  • ISSN
    09168508
  • データ提供元
    CJP書誌  NII-ELS 
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