A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs

• TOGAWA Nozomu

  the Department of Electronics, Information and Communication Engineering, Waseda University

• ARA Koji

  the Department of Electronics, Information and Communication Engineering, Waseda University

• YANAGISAWA Masao

  the Department of Electronics, Information and Communication Engineering, Waseda University

• OHTSUKI Tatsuo

  the Department of Electronics, Information and Communication Engineering, Waseda University

抄録

This paper proposes a fast depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured lookup tables. First, we propose a technology mapping algorithm which minimizes the number of logic-blocks if an input Boolean network is a tree. Second, we propose a technology mapping algorithm which minimizes logic depth for any input Boolean network. Finally, we combine those two technology mapping algorithms and propose an algorithm which realizes technology mapping whose depth is bounded by a given upper bound d_c. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.

収録刊行物

• IEICE transactions on fundamentals of electronics, communications and computer sciences

  IEICE transactions on fundamentals of electronics, communications and computer sciences 82 (3), 473-482, 1999-03-25

  一般社団法人電子情報通信学会

キーワード

• technology mapping
• logic-block
• lookup table
• logic depth

詳細情報

• CRID: 1571698602418918912
• NII論文ID: 110003216572
• NII書誌ID: AA10826239
• ISSN: 09168508
• 本文言語コード: en
• データソース種別:
  • CiNii Articles