Analysis of Buffer Requirement for ATM-LSRs with Partial VC-Merging Capability

  • LIN Po-Chou
    the Wireless Communication Technology Lab., Telecommunication Laboratories, Chunghwa Telecom, Co., Ltd.
  • CHANG Chung-Ju
    the Department of Communication Engineering, Lee and MTI Center for Networking Research, National Chiao Tung University

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Abstract

In an Multi-Protocol Label Switching (MPLS) network domain, Asynchronous Transfer Mode-Label Switch Routers (ATM-LSRs) are considered the best candidate for providing the highest forwarding capability. ATM-LSRs implement a VC-merging scheme that allows many IP routes to be mapped into the same VPI/VCI label, hence supporting scalability. The VC-merging requires reassembly buffers to reconstruct an original packet from its segmented but interleaved AAL-5 cells. In this paper, we analyze the performance of an ATM-LSR with partial VC-merging capability and investigate the impact of VC-merging on the requirement of the reassembly and output buffer. The numerical computation complexity of the mathematical analysis can be reduced from O(M^4) to O(M^2) where M is the total number of ON-OFF sources. We also propose a closed-form equation, which approximates the distribution of the output buffer with satisfactory accuracy. Numerical results show that when incoming cells are severely interleaved, the VC-merging needs the reassembly buffer size to be of the same order as the output buffer size, which cannot be ignored.

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Details

  • CRID
    1570291227535649152
  • NII Article ID
    110003219439
  • NII Book ID
    AA10826261
  • ISSN
    09168516
  • Text Lang
    en
  • Data Source
    • CiNii Articles

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