Trends in Capacitor Dielectrics for DRAMs (Special Issue on LSI Memories)

Material research on capacitor dielectrics for DRAM applications is reviewed. The state of the art technologies to prepare Si_3N_4, Ta_2O_5, and SrTiO_3 thin films for capacitors are described. The down-scaling limits for Si_3N_4 and Ta_2O_5 capacitors seem to be 3.5 and 1.5 nm SiO_2 equivalent thickness, respectively. Combined with a rugged polysilicon electrode surface, Si_3N_4 and Ta_2O_5 based-capacitors are available for 256 Mbit and 1 Gbit DRAMs. At the present time, the minimum SiO_2 equivalent thickness for high permittivity materials is around 1 nm with the leakage current density of 10^<-7> A / cm^2. Among the great variety of ferroelectrics, two families of materials, i.e., Pb (Zr, Ti) O_3 and (Ba, Sr) TiO_3 have emerged as the most promising candidates for 1 Gbit DRAMs and beyond. If the chemical vapor deposition technology can be established for these materials, capacitor dielectrics should not be a limiting issue for Gbit DRAMs.