An Effective Defect-Repair Scheme for a High Speed SRAM (Special Issue on LSI Memories)

To make a fast Bi-CMOS SRAM yield high without speed degradation, three defect-repair methods, the address comparison method, the fuse decoder method and the distributed fuse method, were considered in detail and their advantages and disadvantages were made clear. The distributed fuse method is demonstrated to be further improved by a built-in fuse word driver and a built-in fuse column selector, and fuse analog switches. This enhanced distributed fuse scheme was examined in a fast Bi-CMOS SRAM. A maximum access time of ns and a chip size of 8.8mm×17.4mm are expected for a 4 Mb Bi-CMOS SRAM in the future.