Statistical Memory Yield Analysis and Redundancy Design Considering Fabrication Line Improvement (Special Issue on LSI Memories)

• Imamiya Ken-ichi

  Semiconductor Device Engineering Laboratory, TOSHIBA CORPORATION

• Miyamoto Jun-ichi

  Semiconductor Device Engineering Laboratory, TOSHIBA CORPORATION

• Ohtsuka Nobuaki

  Semiconductor Device Engineering Laboratory, TOSHIBA CORPORATION

• Tomita Naoto

  Semiconductor Device Engineering Laboratory, TOSHIBA CORPORATION

• Iyama Yumiko

  TOSHIBA Microelectronics Corporation

Abstract

The method to optimize redundancy scheme for memory devices is proposed. Yield for new generation memories is predicted by failure mode analysis of previous generation memories. Fabrication line improvement and chip area penalty by the redundancy are taken into account for this yield prediction. The actual data of 16 Mbit EPROM failure analysis indicate the effectiveness of the prediction.

Journal

• IEICE transactions on electronics

  IEICE transactions on electronics 76 (11), 1626-1631, 1993-11-25

  The Institute of Electronics, Information and Communication Engineers

Details

• CRID: 1571135652317614336
• NII Article ID: 110003220067
• NII Book ID: AA10826283
• ISSN: 09168524
• Text Lang: en
• Data Source:
  • CiNii Articles