Read/Search this Article
Abstract
The method to optimize redundancy scheme for memory devices is proposed. Yield for new generation memories is predicted by failure mode analysis of previous generation memories. Fabrication line improvement and chip area penalty by the redundancy are taken into account for this yield prediction. The actual data of 16 Mbit EPROM failure analysis indicate the effectiveness of the prediction.
Journal
- IEICE transactions on electronics [List of Volumes]
-
IEICE transactions on electronics E76-C(11), 1626-1631, 1993-11-25 [Table of Contents]
The Institute of Electronics, Information and Communication Engineers
Share