Circuit and Functional Design Technologies for 2 Mb VRAM (Special Issue on LSI Memories)

• Sato Katsuyuki

  Device Development Center, Hitachi Ltd.

• Ogata Masahiro

  Hitachi VLSI Engineering Corp.

• Matsumoto Miki

  Device Development Center, Hitachi Ltd.

• Hamamoto Ryouta

  Device Development Center, Hitachi Ltd.

• Manita Kiichi

  Hitachi VLSI Engineering Corp.

• Okada Terutaka

  Hitachi VLSI Engineering Corp.

• Sakai Yuji

  Device Development Center, Hitachi Ltd.

• Oishi Kanji

  Device Development Center, Hitachi Ltd.

• Yamamura Masahiro

  Semiconductor & Integrated Circuits Div., Hitachi Ltd.

抄録

Four circuit techniques and a layout design scheme were proposed to realize a 2 Mb VRAM used 0.8 μm technology. They are the enhanced circuit technologies for high speed operation, the functional circuit design and the effective repair schemes for a VRAM, the low power consumption techniques to active and standby mode and a careful layout design scheme realizing high noise immunity. Using these design techniques, a 2 Mb VRAM is suitable for the graphics application of a 512×512×8 pixels basis screen, with a clear mode of 4.6 GByte / sec and a 4-multi column write mode of 400 MByte / sec, even using the same 0.8 μm technology as the previous VRAM (1 Mb) was realized.

収録刊行物

• IEICE transactions on electronics

  IEICE transactions on electronics 76 (11), 1632-1640, 1993-11-25

  一般社団法人電子情報通信学会

詳細情報

• CRID: 1572261552224451584
• NII論文ID: 110003220068
• NII書誌ID: AA10826283
• ISSN: 09168524
• 本文言語コード: en
• データソース種別:
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