Deep Submicron Field Isolation with Buried Insulator between Polysilicon Electrodes (BIPS) (Special Section on High Speed and High Density Multi Functional LSI Memories)

• Shimizu Masahiro

  the ULSI Laboratory, Mitsubishi Electric Corporation

• Inuishi Masahide

  the ULSI Laboratory, Mitsubishi Electric Corporation

• Tsukamoto Katsuhiro

  the Kita-Itami Works, Mitsubishi Electric Corporation

• Arima Hideaki

  the ULSI Laboratory, Mitsubishi Electric Corporation

• Miyoshi Hirokazu

  the ULSI Laboratory, Mitsubishi Electric Corporation

抄録

A novel isolation stucture which has a buried insulator between polysilicon electrodes (BIPS) has been developed. The BIPS isolation employs the refilling CVD-oxides in openings between polysilicon electrodes by photoresist etchback process. Device characteristics and parasitic effects of BIPS isolation have been compared with that of LOCOS isolation. Using BIPS isolation, we can almost suppress the narrowchannel effects and achieve the deep submicron isolation. No degradation on the subthreshold decay of devices with BIPS isolation can be obtained. The use of BIPS isolation technology yields a DRAM cell of small area. The successful fabrication of deep submicron devices with BIPS isolation clearly demonstrates that this technology has superior ability to overcome the LOCOS isolation.

収録刊行物

• IEICE transactions on electronics

  IEICE transactions on electronics 77 (8), 1369-1376, 1994-08-25

  一般社団法人電子情報通信学会

キーワード

• isolation
• parasitic field transistor
• MOSFET

詳細情報

• CRID: 1570291227387745152
• NII論文ID: 110003220486
• NII書誌ID: AA10826283
• ISSN: 09168524
• 本文言語コード: en
• データソース種別:
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