The Phase Locked Loop for Clock Recovery Used in a Single-Chip 4-Channel 155Mb/s CMOS ATM Physical Layer Controller LSI

• NAKAO Takehiko

  Toshiba Corporation

• KUWAHARA Masanori

  Toshiba Corporation

• OHARA Yasuo

  Toshiba Corporation

• ARIYOSHI Reiji

  Toshiba Microelectronics Corporation

• KITAZUME Toshihiko

  Toshiba Microelectronics Corporation

• SUGAWA Naoki

  Toshiba Microelectronics Corporation

• OGAWARA Takeshi

  Toshiba Information Systems Corporation

• ODA Satoshi

  Toshiba Information Systems Corporation

• NOMURA Shoji

  Toshiba Corporation

• MIYAZAWA Yuichi

  Toshiba Corporation

• KANUMA Akira

  Toshiba Corporation

Abstract

The Phase Locked Loop (PLL) for clock recovery used in a single chip 155.52Mb/s×4-Ch CMOS LSI (QPLC) for SONET/SDH termination is described in this letter. This LSI is the first quad-channel ATM physical layer controller chip in which each channel has a clock recovery PLL achieving 55ps rms jitter, using current regulated constant amplitude differential VCO and the triple well structure.

Journal

• IEICE transactions on electronics

  IEICE transactions on electronics 81 (5), 746-749, 1998-05-25

  The Institute of Electronics, Information and Communication Engineers

Keywords

• PLL
• Jitter
• ATM
• OPLC

Details

• CRID: 1572824502177707008
• NII Article ID: 110003220646
• NII Book ID: AA10826283
• ISSN: 09168524
• Text Lang: en
• Data Source:
  • CiNii Articles