Soft-Core Processor Architecture for Embedded System Design

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著者

    • NURPRASETYO Eko Fajar
    • the Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyushu University
    • INOUE Akihiko
    • the Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyushu University
    • TOMIYAMA Hiroyuki
    • the Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyushu University
    • YASUURA Hiroto
    • the Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyushu University

抄録

In the design of an embedded system, an architecture of core processor strongly affects the performance and cost of the total system.This paper discusses a scalable processor architecture, called soft-core processor, which can be tuned for a target system.System designers can optimize several design parameters such as the datapath width and instruction set, and generate customized processors for their application.Design of Bung-DLX as a prototype of soft-core processor is presented in this paper.An experiment of system design using our processor has shown that the optimized processor chip area halves when the critical path delay is reduced to one third of the original one.

収録刊行物

  • IEICE transactions on electronics

    IEICE transactions on electronics 81(9), 1416-1423, 1998-09-25

    一般社団法人電子情報通信学会

参考文献:  11件中 1-11件 を表示

被引用文献:  20件中 1-20件 を表示

各種コード

  • NII論文ID(NAID)
    110003220679
  • NII書誌ID(NCID)
    AA10826283
  • 本文言語コード
    ENG
  • 資料種別
    ART
  • ISSN
    09168524
  • データ提供元
    CJP書誌  CJP引用  NII-ELS 
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