Implementation of a Two-Step SOVA Decoder with a Fixed Scaling Factor(Wireless Communication Technology)

    • KWON Taek-Won
    • School of Electrical Engineering, Kyungpook National University
    • CHOI Jun-Rim
    • Faculty of the School of Electrical Engineering, Kyungpook National University

Abstract

Two implementation schemes for a two-step SOVA (Soft Output Viterbi Algorithm) decoder are proposed arid verified in a chip. One uses the combination of trace back (TB) logic to find the survivor state and double trace back logic to find the weighting factor of a two-step SOVA. The other is that the reliability values are divided by a scaling factor in order to compensate for the distortion brought by overestimating those values in SOVA. We introduced a fixed scaling factor of 0.25 or 0.33 for a rate 1/3 and designed an 8-state Turbo decoder with a 256-bit frame size to lower the reliability values. The implemented architecture of the two-step SOVA decoder allows important savings in area and high-speed processing compared with the one-step SOVA decoder using register exchange (RE) or trace-back (TB) method. The chip is fabricated using 0.65μm gate array at Samsung Electronics and it shows higher SNR performance by 2dB at the BER 10^4 than that of a two-step SOVA decoder without a scaling factor.

Journal

IEICE transactions on communications   [List of Volumes]

IEICE transactions on communications E86-B(6), 1893-1900, 2003-06-01  [Table of Contents]

The Institute of Electronics, Information and Communication Engineers

References:  11

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Codes

  • NII Article ID (NAID) :
    110003221890
  • NII NACSIS-CAT ID (NCID) :
    AA10826261
  • Text Lang :
    ENG
  • Article Type :
    ART
  • ISSN :
    09168516
  • Databases :
    CJP  NII-ELS 

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