Efficient Application of Hot-Carrieer Reliability Simulation to Delay Library Screening for Reliability of Logic Designs

• SATO Hisako

  Semiconductor and Integrated Circuits, Hitachi, Ltd.

• OHTSUKA Mariko

  Hitachi ULSI Systems Co., Ltd.

• MAKABE Kazuya

  Semiconductor and Integrated Circuits, Hitachi, Ltd.

• KONDO Yuichi

  Hitachi ULSI Systems Co., Ltd.

• YANAGISAWA Kazumasa

  Semiconductor and Integrated Circuits, Hitachi, Ltd.

• LEE Peter M.

  Semiconductor and Integrated Circuits, Hitachi, Ltd.

抄録

This paper presents an efficient, application of hot-carrier reliability simulation to delay libraries of 0.18μm and 0.14μm gate length logic products. Using analysis of simple primitive inverter cells, a design rule was developed in restricting signal rise time, and delay libraries of actual products were screened to check whether the rise time restrictions were met. At 200MHz, maximum rise time (0 100%) triseMAX was 0.8nsec (17% of duty) under Δtd/td = 5%. For a 800,000 net product, only 25 simulations were done (each less than one minute CPU time) for the internal devices with screening done for this logic process. 30 nets were caught, but judged reliable due to their reduced duty.

収録刊行物

• IEICE transactions on electronics

  IEICE transactions on electronics 86 (5), 842-849, 2003-05-01

  一般社団法人電子情報通信学会

キーワード

• hot-carrier
• circuit reliability
• simulation
• delay library
• logic design

詳細情報

• CRID: 1573105977154565504
• NII論文ID: 110003223497
• NII書誌ID: AA10826283
• ISSN: 09168524
• 本文言語コード: en
• データソース種別:
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