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Abstract
論理関数を非同期式で実現するためには,その出力の確定を外部回路が知るためにFour-Phase Signaling等のプロトコルを用いる必要がある.本稿では,extended Four-Phase Signalingと呼ばれる,データ表現を2種類用いることにより休止相を隠蔽できるプロトコルに着目し,制御用記憶素子を用いることなしに,すなわち,組み合わせ回路として与えられた論理関数を実現する方法を提案する.まず,このために必要となる符号を定義し,それが組み合わせ回路実現を可能とすることを示す.次に,そのような符号の一つとして4線式符号を取り上げ,一般的なゲートライブラリにのみ含まれる素子を用いて,QDI (Quasi Delay-Insensitive)回路を実現する方法を示す.
For implementing a Boolean function in Self-Timed design, protocols such as Four-phase signaling schemes should be used so that external circuits can notice the completion of the computation of the Boolean function block. In this work, we focus on a protocal called extended Four-Phase signaling scheme, which can hide the resetting phase of Four-Phase signaling scheme by using two different data representations, and propose a generic design style for the memoryless implementation based on the protocal. We first define a combinational delay-insensitive code and a delay-insensitve function, and show that they are feasible for the memoryless implementation of Self-Timed boolean function blocks. Then, a Four-Rail code which satisfies the required condition is discussed, and a design style based on it using standard CAD library for constructing QDI (Quasi Delay-Insensitive) circuits is shown.
Journal
- Technical report of IEICE. FTS [List of Volumes]
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Technical report of IEICE. FTS 99(479), 79-86, 1999-11-27 [Table of Contents]
The Institute of Electronics, Information and Communication Engineers