分割可能バス付きプロセッサアレー上の論理行列積とグラフ問題への応用  [in Japanese] Boolean Matrix Multiplication on a Processor Array with Separable Buses, with Applications to Some Graph Problems  [in Japanese]

Abstract

分割可能バス付きプロセッサアレー上で論理行列積をO (1)時間で計算するアルゴリズムを構成し, グラフの推移閉包, 無向グラフの連結成分抽出, 有向グラフの弱連結及び強連結成分抽出, 非巡回有向グラフのトポロジカルソーテイングをO (log n)時間で実行できることを述べる.

Journal

The Transactions of the Institute of Electronics, Information and Communication Engineers. A   [List of Volumes]

The Transactions of the Institute of Electronics, Information and Communication Engineers. A J82-A(3), 487-491, 1999-03-25  [Table of Contents]

The Institute of Electronics, Information and Communication Engineers

References:  6

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Cited by:  1

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Codes

  • NII Article ID (NAID) :
    110003313302
  • NII NACSIS-CAT ID (NCID) :
    AN10013345
  • Text Lang :
    JPN
  • Article Type :
    Journal Article
  • ISSN :
    09135707
  • NDL Article ID :
    4691412
  • NDL Source Classification :
    ZN33(科学技術--電気工学・電気機械工業--電子工学・電気通信)
  • NDL Call No. :
    Z16-605
  • Databases :
    CJP  CJPref  NDL  NII-ELS 

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