超並列 CMOS Vision Chip : 階層型正則化フィルタ : 視聴覚技術

DOI
  • 松本 隆
    Department of Electrical Engineering, Waseda University
  • Abidi A.A.
    Department of Electrical Engineering, University of California
  • 新見 琢司
    Department of Electrical Engineering, Waseda University
  • 小林 春夫
    Electronics Research Laboratory, Yokogawa Electric Corporation
  • 八木 哲也
    Department of Control Engineering and Science, Kyusyu Institute of Technology
  • 沢地 利明
    Department of Electrical Engineering, Waseda University

書誌事項

タイトル別名
  • A Massively Parallel CMOS Vision Chip : Double-layer Regularization Filter

抄録

This paper is an implementation version of our algorithm proposed in [2]. The chip implemented solves first and second order regularization problems simultaneously which, in turn, enhances contrasts of images after smoothing. A 2μm standard CMOS technology was used with double metal and single poly. The computation is done by the dynamics and its execution time is within several micro seconds.

収録刊行物

詳細情報 詳細情報について

  • CRID
    1390282679497585280
  • NII論文ID
    110003685552
  • DOI
    10.11485/tvtr.16.79_13
  • ISSN
    24330914
    03864227
  • 本文言語コード
    en
  • データソース種別
    • JaLC
    • CiNii Articles
  • 抄録ライセンスフラグ
    使用不可

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