超並列 CMOS Vision Chip : 階層型正則化フィルタ : 視聴覚技術
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- 松本 隆
- Department of Electrical Engineering, Waseda University
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- Abidi A.A.
- Department of Electrical Engineering, University of California
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- 新見 琢司
- Department of Electrical Engineering, Waseda University
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- 小林 春夫
- Electronics Research Laboratory, Yokogawa Electric Corporation
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- 八木 哲也
- Department of Control Engineering and Science, Kyusyu Institute of Technology
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- 沢地 利明
- Department of Electrical Engineering, Waseda University
書誌事項
- タイトル別名
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- A Massively Parallel CMOS Vision Chip : Double-layer Regularization Filter
抄録
This paper is an implementation version of our algorithm proposed in [2]. The chip implemented solves first and second order regularization problems simultaneously which, in turn, enhances contrasts of images after smoothing. A 2μm standard CMOS technology was used with double metal and single poly. The computation is done by the dynamics and its execution time is within several micro seconds.
収録刊行物
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- テレビジョン学会技術報告
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テレビジョン学会技術報告 16 (79), 13-18, 1992
一般社団法人 映像情報メディア学会
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詳細情報 詳細情報について
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- CRID
- 1390282679497585280
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- NII論文ID
- 110003685552
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- ISSN
- 24330914
- 03864227
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- CiNii Articles
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- 抄録ライセンスフラグ
- 使用不可