不連続再収斂構造に基づくパス遅延故障に対する部分拡張スキャン設計法  [in Japanese] A Method of Partially Enhanced Scan Design for Path Delay Faults Based on Discontinuous Reconvergence Structure  [in Japanese]

本稿では,パス遅延故障に対してテスト生成が容易な順序回路の構造として,不連続再収斂構造を提案し,不連続再収斂順序回路のパス遅延故障に対するテスト生成法を示す.また,不連続再収斂順序回路におけるパス遅延故障に対するテスト生成問題が,その時間展開モデルにおけるセグメント遅延故障に対するテスト生成問題に帰着できることを示す.さらに本稿では,不連続再収斂構造に基づく部分拡張スキャン設計法も提案する.

In this paper, we present a new structure of sequential circuits with easy testability for path delay faults. The structure is called discontinuous reconvergence structure. We propose a method of path delay test generation in sequential circuits with discontinuous reconvergence structure. We show that the test generation problem for path delay faults in sequential circuits with discontinuous reconvergence structure can be reduced to the test generation problem for segment delay faults in its time expansion model. In addition, we also propose a method of partially enhanced scan design based on discontinuous reconvergence structure.