アナログDCT演算回路による画像圧縮センサの検討  [in Japanese] An Image Compression Sensor with Analog DCT Operations  [in Japanese]

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Author(s)

    • 坂井丈泰 Sakai Takeyasu
    • 早稲田大学理工学部電気電子情報工学科 Department of Electrical, Electroincs and Computer Engineering, Waseda University
    • 永井 宏昌 Nagai Hiromasa
    • 早稲田大学理工学部電気電子情報工学科 Department of Electrical, Electroincs and Computer Engineering, Waseda University
    • 松本 隆 Mastumoto Takashi
    • 早稲田大学理工学部電気電子情報工学科 Department of Electrical, Electroincs and Computer Engineering, Waseda University

Abstract

A parallel architecture is proposed for analog DCT operations using floating-gate transistors with differential inputs and feedback. All operations are in voltage mode. Only one terminal is required for the feedback which is capable of suppressing the distortions due to active elements. Implementing DCT operation circuits together with an array of photosensors, an image compression sensor can be realized.

Journal

  • 1996年度テレビジョン学会年次大会講演予稿集, 7月

    1996年度テレビジョン学会年次大会講演予稿集, 7月, 41-42, 1996

    The Institute of Image Information and Television Engineers

Cited by:  1

  • Low-Power neuron-MOS Logic Gate  [in Japanese]

    KWON Ho-yup , SHIBATA Tadashi , OHMI Tadahiro

    Technical report of IEICE. SDM 96(360), 31-38, 1996-11-15

    References (22)

Codes

  • NII Article ID (NAID)
    110004778982
  • NII NACSIS-CAT ID (NCID)
    AN10492168
  • Text Lang
    JPN
  • Article Type
    Proceedings
  • ISSN
    09191879
  • Data Source
    CJPref  NII-ELS 
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