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Abstract
Two wrapper architectures (Type 1 and Type 2) are proposed in order to efficiently reuse the Networks-on-Chip (NoC) channels for test vectors and responses transportation between a test source/sink to a core-under-test. The proposed Type 1 NoC wrapper makes use of the NoC's guaranteed bandwidth to ensure data integrity. The wrapper efficiently utilizes the allocated NoC bandwidth for some configurations of the NoC-core interface architecture, with minimal area overhead. For other NoC-core configurations, in which the Type 1 is unable to efficiently operate, a Type 2 NoC wrapper is proposed. The added advantage is achieved by an enhanced interface at a cost of slightly higher area overhead. The trade-off between the Type 1 and the Type 2 NoC wrappers are evaluated using two optimization algorithms under channel bandwidth constraint and test time constraint, respectively. The experimental results show that the use of two complementary wrappers allows an efficient reuse of the functional NoC for core-based tests, with very little or no increase in the test application time compared to the TAM-based approaches.
Journal
- IEICE technical report. Dependable computing [List of Volumes]
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IEICE technical report. Dependable computing 106(528), 1-6, 2007-02-02 [Table of Contents]
The Institute of Electronics, Information and Communication Engineers