NoC Wrapper Optimization under Channel Bandwidth and Test Time Constraints

    • YONEDA Tomokazu
    • Graduate School of Information Science, Nara Institute of Science and Technology
    • FUJIWARA Hideo
    • Graduate School of Information Science, Nara Institute of Science and Technology

Abstract

Two wrapper architectures (Type 1 and Type 2) are proposed in order to efficiently reuse the Networks-on-Chip (NoC) channels for test vectors and responses transportation between a test source/sink to a core-under-test. The proposed Type 1 NoC wrapper makes use of the NoC's guaranteed bandwidth to ensure data integrity. The wrapper efficiently utilizes the allocated NoC bandwidth for some configurations of the NoC-core interface architecture, with minimal area overhead. For other NoC-core configurations, in which the Type 1 is unable to efficiently operate, a Type 2 NoC wrapper is proposed. The added advantage is achieved by an enhanced interface at a cost of slightly higher area overhead. The trade-off between the Type 1 and the Type 2 NoC wrappers are evaluated using two optimization algorithms under channel bandwidth constraint and test time constraint, respectively. The experimental results show that the use of two complementary wrappers allows an efficient reuse of the functional NoC for core-based tests, with very little or no increase in the test application time compared to the TAM-based approaches.

Journal

IEICE technical report. Dependable computing   [List of Volumes]

IEICE technical report. Dependable computing 106(528), 1-6, 2007-02-02  [Table of Contents]

The Institute of Electronics, Information and Communication Engineers

References:  22

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Codes

  • NII Article ID (NAID) :
    110006224499
  • NII NACSIS-CAT ID (NCID) :
    AA11645397
  • Text Lang :
    ENG
  • Article Type :
    ART
  • ISSN :
    09135685
  • NDL Article ID :
    8677349
  • NDL Source Classification :
    ZN33(科学技術--電気工学・電気機械工業--電子工学・電気通信)
  • NDL Call No. :
    Z16-940
  • Databases :
    CJP  NDL  NII-ELS