同時多重に発生する過渡故障を考慮した高信頼化順序回路(ディペンダブルコンピュータシステムとセキュリティ技術及び一般)  [in Japanese] Highly Reliable Sequential Circuits Considering Multiple Simultaneous Transient Faults  [in Japanese]

Abstract

過渡故障が同時多重に発生する事態を想定して,時間冗長ならびに空間冗長適用することで順序回路を高信頼化する手法を提案する.具体的な故障モデルとしては,組み合わせ回路部分の信号線から乗ったノイズが複数のフリップフロップに取り込まれるものを仮定する.

This paper proposes a novel technique to improve the reliability of sequential circuits. The proposed technique adopts the space-time redundancy which improves the reliability to multiple transient faults. The supposed fault model for this technique is the one in which multiple flip-flop circuits receive wrong data due to noise through signal lines of combinational circuits.

Journal

IEICE technical report. Dependable computing   [List of Volumes]

IEICE technical report. Dependable computing 109(12), 1-6, 2009-04-14  [Table of Contents]

The Institute of Electronics, Information and Communication Engineers

References:  4

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Codes

  • NII Article ID (NAID) :
    110007226034
  • NII NACSIS-CAT ID (NCID) :
    AA11645397
  • Text Lang :
    JPN
  • Article Type :
    ART
  • ISSN :
    09135685
  • NDL Article ID :
    10221653
  • NDL Source Classification :
    ZN33(科学技術--電気工学・電気機械工業--電子工学・電気通信)
  • NDL Call No. :
    Z16-940
  • Databases :
    CJP  NDL  NII-ELS