Evaluation of Digitally Controlled PLL by Clock-Period Comparison

• MAKIHARA Yukinobu

  the Graduate School of Information Science and Technology, Hokkaido University

• IKEBE Masayuki

  the Graduate School of Information Science and Technology, Hokkaido University

• SANO Eiichi

  Research Center for Integrated Quantum Electronics, Hokkaido University

抄録

For a digitally controlled phase-locked loop (PLL), we evaluate the use of a clock-period comparator (CPC). In this PLL, only the frequency lock operation should be performed; however, the phase lock operation is also simultaneously achieved by performing the clock-period comparison when the phases of the reference signal and the output signal approach each other. Theoretically a lock-up operation was conducted. In addition, we succeeded in digitizing a voltage controlled oscillator (VCO) with a linear characteristic. We confirmed a phase lock operation with a slight loop characteristic through SPICE simulation.

収録刊行物

• IEICE transactions on electronics

  IEICE transactions on electronics 90 (6), 1307-1310, 2007-06-01

  一般社団法人電子情報通信学会

キーワード

• digitally controlled PLL
• clock-period comparator
• loop characteristic
• loop filter

詳細情報

• CRID: 1570291227578847360
• NII論文ID: 110007519709
• NII書誌ID: AA10826283
• ISSN: 09168524
• 本文言語コード: en
• データソース種別:
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