A sub-mW H.264 baseline-profile motion estimation processor core with a VLSI-oriented block partitioning strategy and SIMD/systolic-array architecture

• Miyakoshi Junichi

• Murachi Yuichiro

• Matsuno Tetsuro

• Hamamoto Masaki

• Iinuma Takahiro

• Ishihara Tomokazu

• Kawaguchi Hiroshi

• Miyama Masayuki

• Yoshimoto Masahiko

• 深山 正幸

• 吉本 雅彦

抄録

金沢大学理工研究域電子情報学系

We propose a sub-mW H.264 baseline-profile motion estimation processor for portable video applications. It features a VLSI-oriented block partitioning strategy and low-power SIMD/systolic-array datapath architecture, where the datapath can be switched between an SIMD and systolic array depending on processing flow. The processor supports all the seven kinds of block modes, and can handle three reference frames for a CIF (352 × 288) 30-fps to QCIF (176 × 144) 15-fps sequences with a quarter-pixel accuracy. It integrates 3.3 million transistors, and occupies 2.8×3.1 mm2 in a 130-nm CMOS technology. The proposed processor achieves a power of 800 μW in a QCIF 15-fps sequence with one reference picture. Copyright © 2006 The Institute of Electronics, Information and Communication Engineers.

収録刊行物

• IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A (12), 3623-3633, 2006-12-01

  IEICE 電子情報通信学会

キーワード

• H.264
• Low power
• Motion estimation
• SIMD
• Systolic array

詳細情報

• CRID: 1390295116813761664
• NII論文ID: 110007537867
• NII書誌ID: AN10467885
• ISSN: 09168508
• DOI: 10.24517/00009971
• Web Site: http://hdl.handle.net/2297/24651
• 本文言語コード: en
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