A Fine-Grain Scalable and Low Memory Cost Variable Block Size Motion Estimation Architecture for H.264/AVC

• LIU Zhenyu

  Kitakyushu Foundation for the Advancement of Industry Science and Technology

• SONG Yang

  IPS, Waseda University

• IKENAGA Takeshi

  IPS, Waseda University

• GOTO Satoshi

  IPS, Waseda University

抄録

One full search variable block size motion estimation (VBSME) architecture with integer pixel accuracy is proposed in this paper. This proposed architecture has following features: (1) Through widening data path from the search area memories, m processing element groups (PEG) could be scheduled to work in parallel and fully utilized, where m is a factor of sixteen. Each PEG has sixteen processing elements (PE) and just costs 8.5K gates. This feature provides users more flexibility to make tradeoff between the hardware cost and the performance. (2) Based on pipelining and multi-cycle data path techniques, this architecture can work at high clock frequency. (3) The memory partition number is greatly reduced. When sixteen PEGs are adopted, only two memory partitions are required for the search area data storage. Therefore, both the system hardware cost and power consumption can be saved. A 16-PEG design with 48×32 search range has been implemented with TSMC 0.18μm CMOS technology. In typical work conditions, its maximum clock frequency is 261MHz. Compared with the previous 2-D architecture, about 13.4% hardware cost and 5.7% power consumption can be saved.

収録刊行物

• IEICE transactions on electronics

  IEICE transactions on electronics 89 (12), 1928-1936, 2006-12-01

  一般社団法人電子情報通信学会

キーワード

• H.264
• AVC
• variable block size motion estimation
• VLSI architecture

詳細情報

• CRID: 1571980077498439936
• NII論文ID: 110007538752
• NII書誌ID: AA10826283
• ISSN: 09168524
• 本文言語コード: en
• データソース種別:
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