A Non-snapback NMOS ESD Clamp Circuit using Gate-Coupled Scheme with Isolated Well in a Bipolar-CMOS-DMOS Process(Session 7B : Si IC and Circuit Technology)
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A novel non-snapback NMOS Electrostatic Discharge (ESD) clamp circuit is proposed in a 0.35 μm Bipolar-CMOS-DMOS (BCD) process. The proposed ESD clamp has a non-snapback characteristics using gate-coupled effect. This proposed ESD clamp circuit is developed without additional components due to replace a capacitor with an isolated parasitic capacitor. This proposed ESD clamp circuit consists of NMOS transistors with a Slicide blocking layer and a Poly resistor. The result of the proposed ESD clamp circuit is measured by 100 ns Transmission Line Pulse (TLP) system. From the measurement, it was observed that the proposed ESD clamp has approximately 50% lower triggering voltage compared to the conventional gate-grounded NMOS ESD clamp without degradation of the other ESD design key parameter.