%A PARK, Jae-Young
%A KIM, Dae-Woo
%A SON, Young-Sang
%A HA, Jong-Chan
%A SONG, Jong-Kyu
%A JANG, Chang-Soo
%A JUNG, Won-Young
%T A Non-snapback NMOS ESD Clamp Circuit using Gate-Coupled Scheme with Isolated Well in a Bipolar-CMOS-DMOS Process(Session 7B : Si IC and Circuit Technology)
%J 電子情報通信学会技術研究報告. SDM, シリコン材料・デバイス
%0 Journal Article
%@ 09135685
%I 一般社団法人電子情報通信学会
%D 2010
%8 2010-06-23
%V 110
%N 110
%P 269-274
%U http://ci.nii.ac.jp/naid/110007890323/
%R