CBM: Core Based Memory Scheduling method

• Kohei Hosokawa

• Yasuo Ishii

• Mary Inaba

• Kei Hiraki

抄録

In modern chip-multiprocessor systems，DRAM is shared among multiple threads．The memory scheduler must resolve the inter-thread contention for the DRAM effectiveness．Previously proposed DRAM memory schedulers have calculated the memory access intensity of each thread for the priority scheduling．Existing methods [2]，[3] analyze the number of memory requests served in memory controller to get memory-intensity，but these methods lack prediction accuracy．TCM [1] avoids this problem by using MPKI information．TCM can improve the prediction accuracy，but takes very long cycles to update the thread priority．As a result, TCM lacks the timeliness of the priority prediction．This paper presents a new memory scheduling method，Core-Based Memory scheduling (CBM)，which utilizes core information for memory-intensity evaluation of each thread. Our key idea is 1) to refer the distance of instruction count between each memory request for the priority calculation, and 2) to place the priority scheduler on each core．CBM judges the core calculation progress by comparing the instruction counter distance between the new memory request and the last one．By doing so，CBM can utilize the instruction progress information of each core directly，thus we can predict the memory-intensity more accurately．CBM also proposes to calculate the thread priority not on the memory controller but on the private cache of each core．By doing so, even in concurrent many-channel memory system，CBM can decide priority without the heavy inter-channel communication．Therefore, CBM accomplishes high timeliness on the priority update．We evaluate CBM by using the workloads of Memory Scheduling Championship (MSC) and compare its performance to two existing scheduling algorithms. We found that CBM achieves both the best throughput and fairness．In modern chip-multiprocessor systems，DRAM is shared among multiple threads．The memory scheduler must resolve the inter-thread contention for the DRAM effectiveness．Previously proposed DRAM memory schedulers have calculated the memory access intensity of each thread for the priority scheduling．Existing methods [2]，[3] analyze the number of memory requests served in memory controller to get memory-intensity，but these methods lack prediction accuracy．TCM [1] avoids this problem by using MPKI information．TCM can improve the prediction accuracy，but takes very long cycles to update the thread priority．As a result, TCM lacks the timeliness of the priority prediction．This paper presents a new memory scheduling method，Core-Based Memory scheduling (CBM)，which utilizes core information for memory-intensity evaluation of each thread. Our key idea is 1) to refer the distance of instruction count between each memory request for the priority calculation, and 2) to place the priority scheduler on each core．CBM judges the core calculation progress by comparing the instruction counter distance between the new memory request and the last one．By doing so，CBM can utilize the instruction progress information of each core directly，thus we can predict the memory-intensity more accurately．CBM also proposes to calculate the thread priority not on the memory controller but on the private cache of each core．By doing so, even in concurrent many-channel memory system，CBM can decide priority without the heavy inter-channel communication．Therefore, CBM accomplishes high timeliness on the priority update．We evaluate CBM by using the workloads of Memory Scheduling Championship (MSC) and compare its performance to two existing scheduling algorithms. We found that CBM achieves both the best throughput and fairness．

収録刊行物

• 研究報告計算機アーキテクチャ（ARC）

  研究報告計算機アーキテクチャ（ARC） 2012 (9), 1-6, 2012-07-25

詳細情報

• CRID: 1572261552753004032
• NII論文ID: 110009425021
• NII書誌ID: AN10096105
• 本文言語コード: en
• データソース種別:
  • CiNii Articles