Column parallel SS-ADC with TDC using multi-phase clock signals for CMOS imagers(Circuit technologies,2nd Asian Image Sensors and Imaging Systems Symposium)

• Ikebe Masayuki

  Graduate School of Information Science and Technology, Hokkaido University

• Uchida Daisuke

  Graduate School of Information Science and Technology, Hokkaido University

• Someya Makito

  Graduate School of Information Science and Technology, Hokkaido University

• Watanabe Kaori

  Graduate School of Information Science and Technology, Hokkaido University

• Kinoshita Koudai

  Graduate School of Information Science and Technology, Hokkaido University

• Chikuda Satoshi

  Graduate School of Information Science and Technology, Hokkaido University

• Motohisa Juinichi

  Graduate School of Information Science and Technology, Hokkaido University

抄録

We propose a single-slop ADC with a time to digital converter (TDC) that uses a multi-phase clock. When the TDC with resolution of n bits is adapted to the ADC, the conversion time is reduced by a factor of 2^n. Applying the TDC that uses multi-phase-clock signal reduced the number of circuit elements, achieved consistency between the single-slope ADC and the TDC, and realized robust meta-stability.

収録刊行物

• 映像情報メディア学会技術報告

  映像情報メディア学会技術報告 38.47 (0), 13-14, 2014

  一般社団法人 映像情報メディア学会

キーワード

• single-slop ADC
• TDC
• multi-phase-clock signal
• meta-stability

詳細情報

• CRID: 1390001204530397696
• NII論文ID: 110009900468
• DOI: 10.11485/itetr.38.47.0_13
• ISSN: 24241970
• ISSN: 13426893
• 本文言語コード: en
• データソース種別:
  • JaLC
  • CiNii Articles
• 抄録ライセンスフラグ: 使用不可