Automatic instrumentation of profilers for FPGA-based design space exploration

• Shibata, Seiya

• Ando, Yuki

• Honda, Shinya

• Tomiyama, Hiroyuki

• Takada, Hiroaki

抄録

In the system-level design of MPSoCs (multi-processor system-on-a-chips), system designers start from describing functionalities of the system as processes and channels, and then decide mapping of them to various processing elements (PEs) including CPUs and dedicated hardware modules. A mapping decision is evaluated by simulation or FPGA-based prototyping. Designers iterate mapping and evaluation until all design requirements are met. We have developed two profilers, a process profiler and a memory profiler, for FPGA-based performance analysis of design candidates. The process profiler records a trace of process activations, while the memory profiler records a trace of channel accesses. According to mapping of processes to PEs, the profilers are automatically configured and instrumented into FPGA-based system prototypes by a system-level design tool that we have developed. Designers therefore need to manually modify neither the system description nor the profilers upon each change of process mapping. In order to demonstrate the effectiveness of our profilers, a case study on MPEG4 decoder design was conducted.

収録刊行物

• International Conference on Field-Programmable Technology (FPT 2009)

  International Conference on Field-Programmable Technology (FPT 2009) 292-295, 2009-12-09

  IEEE

詳細情報

• CRID: 1050564288753641088
• NII論文ID: 120002277493
• HANDLE: 2237/13976
• Web Site: https://nagoya.repo.nii.ac.jp/records/12098
• 本文言語コード: en
• 資料種別: journal article
• データソース種別:
  • IRDB
  • CiNii Articles