An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs

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  • IMAGAWA Takashi
    Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University
  • HIROMOTO Masayuki
    Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University
  • OCHI Hiroyuki
    Department of Computer Science, College of Information Science and Engineering, Ritsumeikan University
  • SATO Takashi
    Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University

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Time redundancy is sometimes an only option for enhancing circuit reliability when the circuit area is severely restricted. In this paper, a time-redundant error-correction scheme, which is particularly suitable for coarse-grained reconfigurable arrays (CGRAs), is proposed. It judges the correctness of the executions by comparing the results of two identical runs. Once a mismatch is found, the second run is terminated immediately to start the third run, under the assumption that the errors tend to persist in many applications, for selecting the correct result in the three runs. The circuit area and reliability of the proposed method is compared with a straightforward implementation of time-redundancy and a selective triple modular redundancy (TMR). A case study on a CGRA revealed that the area of the proposed method is 1% larger than that of the implementation for the selective TMR. The study also shows the proposed scheme is up to 2.6x more reliable than the full-TMR when the persistent error is predominant.

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