All-digital ramp waveform generator for two-step single-slope ADC

• Iizuka Tetsuya

  VLSI Design and Education Center (VDEC), University of Tokyo

• Asada Kunihiro

  VLSI Design and Education Center (VDEC), University of Tokyo

抄録

This paper presents an all-digital on-chip ramp waveform generator for an 8-bit single-slope ADC. The proposed ramp waveform generator consists of static CMOS digital circuits and is designed using standard cells aiming for the process portability. The proposed circuit realizes digitally-controlled ramp output and also realizes two step coarse-fine ramp waveform to speed up the single-slope analog-to-digital conversion. The experimental results of the circuit simulation with random variation on 0.18µm CMOS process demonstrate the feasibility of our ramp waveform generator and 8-bit two-step single-slope ADC with DNL within ±0.2LSB and INL within ±0.8LSB.

収録刊行物

• IEICE Electronics Express

  IEICE Electronics Express 8 (1), 20-25, 2011

  一般社団法人 電子情報通信学会

キーワード

• analog-to-digital converter
• single-slope ADC
• ramp waveform generator
• all-digital

詳細情報

• CRID: 1390282680189293440
• NII論文ID: 130000401459
• DOI: 10.1587/elex.8.20
• ISSN: 13492543
• Web Site: http://www.jstage.jst.go.jp/article/elex/8/1/8_1_20/_pdf
• 本文言語コード: en
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